The present disclosure relates generally to a communication interface of an integrated circuit or die that couples to an additional integrated circuit or die. More particularly, the present disclosure relates to enabling both master-to-master and slave-to-master communication between the interface and the additional integrated circuit.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
An integrated circuit or die may include an interface to communicatively couple the integrated circuit or die to another electronic component. For example, a field-programmable gate array (FPGA) may include a communication interface that communicably couples to a memory device. When coupled, the communication interface may act as a master in a master-to-slave communication relationship with the memory device. That is, the communication interface may control the memory device (e.g., such that the communication interface acts as the master and the memory device acts as a slave). For example, the communication interface may initiate memory transactions and the memory device may respond accordingly.
When the FPGA is communicatively coupled to an additional integrated circuit (e.g., another FPGA, an application-specific integrated circuit (ASIC), an application specific standard product (ASSP), and the like), the communication interface may or may not act as the master. For example, the communication interface may act as the slave while the additional integrated circuit may act as the master. That is, the additional integrated circuit may issue commands to the communication interface. As another example, both the communication interface and the additional integrated circuit may act as masters. That is, the communication interface may issue commands to the additional integrated circuit, and the additional integrated circuit may also issue commands to the communication interface. However, the communication interface may receive the commands from the additional integrated circuit without knowledge of when the commands will arrive, resulting in synchronization problems.
Additionally, the commands may be issued using a free running clock (e.g., such that a write clock includes regular pulses) or a strobe-based clock (e.g., such that the write clock only includes pulses when writing is desired or enabled). The communication interface may not know in advance which clocking scheme the additional integrated circuit is using to issue commands.
Moreover, the communication interface may store the commands and/or associated data in input/output circuitry of the communication interface. The communication interface may bond multiple input/output circuitries to store commands and/or associated data that span a large width. However, enabling storage by bonding multiple input/output circuitries may undesirably increase peak current consumption of the communication interface.